1. Field of the Invention
This invention relates in general to a semiconductor device isolation process, and more particularly to a shallow trench isolation (STI) process utilized in semiconductor device manufacture.
2. Description of Related Art
With the continual improvement of semiconductor integrated circuit (IC) fabrication techniques, the number of devices which can be packed onto a semiconductor chip has increased greatly, while the size of the individual devices has decreased markedly. Today several million devices can be fabricated on a single chip. Consider, for example, mega-bit memory chips which are commonly used today in personal computers and in other applications. In such high-density memory chips, elements must be properly isolated in order to obtain good performance. The main purpose of device isolation techniques is to provide sufficient electrical insulation between the elements of the devices without using a significant amount of area on the chip. In this way, more space is available for other devices and components.
The so-called Local Oxidation of Silicon (LOCOS) technique has been widely used to form a field oxide for device isolation. In today's deep sub-micron manufacturing process (features sized below 0.25 .mu.m), however, using the LOCOS technique results in several drawbacks. First, a relatively large device area is needed and an uneven surface is produced during forming of the field oxide by the LOCOS process. Furthermore, the so-called "bird's beak effect" inevitably appears during forming of the field oxide. Because the bird's beak length is difficult to control within 800 .ANG. when using the LOCOS process, a new shallow trench isolation (STI) technique is generally used for the manufacture of semiconductor devices with feature sized below 0.25 .mu.m.
In a conventional shallow trench isolation (STI) process, an anisotropic dry etching is first performed to form a trench in a silicon substrate having a depth between 0.3 to 0.8 .mu.m. A chemical vapor deposition (CVD) process is then performed to form a silicon oxide layer overlaying the entire silicon substrate. The silicon oxide layer is etched back to the top surface of the silicon substrate with a portion of the oxide layer retained within the trench. The STI process has the advantages of preventing the "bird's beak effect" and reducing cross-disturbance between adjacent electric fields. Therefore, the STI process is applicable in fabricating deep sub-micron semiconductor devices, so as to prevent the occurrence of punch through or latch out.
FIGS. 1A to 1C illustrate the processing steps for a conventional shallow isolation trench. A pad oxide layer 12 and a silicon nitride (Si.sub.3 N.sub.4) layer 14 are first formed on a silicon substrate 10 (FIG. 1A). Photolithography and etching processes are performed to define the pattern of the silicon nitride layer 14, which exposes an area that will form a trench (FIG. 1B). Using the silicon nitride layer 14 as a mask, an anisotropic etching process, such as a reactive ion etching (RIE) is then performed to form a shallow trench 16 in the silicon substrate 10 (FIG. 1C).
The top corner profile of the trench is sharp since it is formed by an anisotropic etching process. This sharp profile causes the previously formed gate oxide layer to have an irregular thickness. Thus, the electric field at the area near the trench corner is larger than that of other areas, resulting in current leakage in the devices. Furthermore, gate oxide layer defects are generally found since a large amount of stress is concentrated near the top corner of the shallow trench 16.